freescale 公司的mc9s08mp16是低成本8位mcu,用于工业和汽车中夹种速度的马达控制,能提供安全的,精确和低成本的马达控制. mc9s08mp16采用8位hcs08 cpu,2.7v-5.5v和–40℃到125℃温度范围内,cpu速度高达40 mhz,支持48个中断/重置源, 16kb 闪存, 1kb ram,马达控制专用的1x 2-ch + 1x 6ch flextimer,3x高速模拟比较器,可编程增益放大器,2x可编程延迟区块,13路12位2.5us转换时间的adc.本文介绍了mc9s08mp16主要特性, 方框图和demo9s08mp16 评估板详细电路图.
the s08mp16 is a low cost 8-bit mcu that delivers safe, accurate and inexpensive motor control for a wide speed range of industrial and automotive applications. an ideal entry-level solution for brushless dc (bldc) motor applications it features an 8 channel pwm/flextimer module providing hardware dead-time insertion, analogue comparators, programmable gain amplifier, and a 12-bit adc with pwm hardware triggering. also offered is an independently clocked cop & cyclic redundancy check (crc) engine providing clock failure protection & memory content validation for safety-critical applications implementing iec60730.
mc9s08mp16主要特性:
• 8-bit hcs08 central processor unit (cpu)
– up to 51.34 mhz cpu at 2.7v to 5.5v across temperature range of –40°c to 105℃
– up to 40 mhz cpu at 2.7v to 5.5v across temperature range of –40°c to 125℃
– hc08 instruction set with added bgnd instruction and additional addressing modes for ldhx and sthx support for up to 48 interrupt/reset sources
• on-chip memory
– up to 16 kb flash memory; read/program/erase over full operating voltage and temperature
– up to 1 kb random-access memory (ram)
– security circuitry to prevent unauthorized access to ram and flash memory contents
• power-saving modes
– two low power stop modes; reduced power wait mode
– peripheral clock gating can disable clocks to unused modules
• clock source options
– oscillator (xosc) — loop-control pierce oscillator; crystal or ceramic resonator range of 31.25–38.4 khz or 1–16 mhz
– internal clock source (ics) — containing a frequency-locked-loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolutions and 2% deviation over temperature and voltage; supports cpu frequencies up to 51.34 mhz
• system protection
– watchdog computer operating properly (cop) reset running from dedicated 1-khz internal clock source or bus clock
– low-voltage detection with reset or interrupt; selectable trip points
– illegal opcode and illegal address detection with reset
– flash memory block protection
• development support
– single-wire background debug interface
– breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus three more breakpoints in on-chip debug module)
– on-chip in-circuit emulator (ice) debug module containing three comparators and nine trigger modes. eight deep fifo for storing change-of-flow addresses and event-only data. debug module supports both tag and force breakpoints
• peripherals
– ipc — interrupt priority controller with 4 programmable interrupt priority levels
– adc—13-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mv/℃ temperature sensor; internal bandgap reference channel; operation in stop3
– pga — differential programmable gain amplifier with programmable gain (x1, x2, x4, x8, x16, or x32)
– hscmp — three fast analog comparators with positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering; windowing; hscmp1 and hscmp2 outputs can be optionally routed to ftm1 module; runs in stop3
– dac — three 5-bit digital to analog convertor used as a 32-tap voltage reference for each comparator
– pdb — two programmable delay blocks: pdb1 synchronizes pwm with samples of adc; pdb2 synchronizes pwm with comparing window of analog comparators
– sci — full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake up on active edge
– spi — full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting
– iic/smbus — up to 400 kbps; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing; smbus compatible
– ftm — two flextimers with total of 8 channels; one 2-channel (ftm1) and one 6-channel (ftm2);supports operation up to 2x bus clock; selectable input capture, output compare, edge- or center-aligned pwm; dead time insertion; fault inputs
– mtim — 8-bit modulo counter with 8-bit prescaler
– rtc — (real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components, runs in all mcu modes
– crc — cyclic redundancy check generator
– kbi — three 8 channel keyboard interrupt module with software selectable polarity on edge or edge/level modes
• input/output
– 40 gpios, 2 output-only pins.
– hysteresis and configurable pull up device on input pins; configurable slew rate and drive strength on output pins; sink/source current up to 20ma
• package options
– 48-lqfp, 32-lqfp, 28-soic 48-lqfp qualified for automotive usage
mc9s08mp16目标应用:
industrial drives/fans/pumps
hvac systems
actuator systems
medical equipment (infusion pumps, respirators, analyzers)
office equipment
small appliance/personal care (food processors, shavers)
automotive electrical fuel pump
automotive window lift
automotive fan control
automotive high-brightness leds
图1.mc9s08mp16系列方框图
图2.demo9s08mp16 评估板外形图
the demo9s08mp16 is a cost-effective demo platform for evaluating and developing with the freescale mc9s08mp16. this low-cost 8-bit mcu is designed to deliver smooth, efficient and safe sensorless bldc motor control across a wide speed range of industrial and automotive applications.
peripherals include but are not limited to two 16-bit flextimers with deadtime insertion and fault protection in hardware, three high-speed analog comparators, a 6-ch., 16-bit pwm module with emergency over-current shutdown protection, a programmable gain amplifier and a 12-ch., 12-bit adc with pwm hardware triggering. also included are an independently clocked cop and cyclic redundancy check (crc) engine delivering clk failure protection and memory content validation for safety-critical applications.
图3.demo9s08mp16 评估板电路图(1)
图4.demo9s08mp16 评估板电路图(2)
图5.demo9s08mp16 评估板电路图(3)
图6.demo9s08mp16 评估板电路图(4)
图7.demo9s08mp16 评估板电路图(5)
图8.demo9s08mp16 评估板电路图(6)
图9.demo9s08mp16 评估板电路图(7)
图10.demo9s08mp16 评估板电路图(8)
图11.demo9s08mp16 评估板电路图(9)
图12.demo9s08mp16 评估板电路图(10)
