There is a continual push for higher efficiencies in power-converter design. In addition, the need to support high levels of energy efficiency in computational processing has led to the creation of loads with highly dynamic behavior, with processors and peripherals activating and deactivating based on their workload. This is driving a change in power converter architecture away from analog to digital implementation.
The operation of a switched-mode power converter looks to be digital in nature as it relies on the transfer of discrete charge packets from one side of the converter to another. The technique is largely based on sampling the state of the output at discrete points in time to determine for how long the switch that delivers charge should be kept on. However, despite this apparent digital structure most implementations are based on analog control circuitry.
Under the pulse-width modulation (PWM) scheme employed by most switched-mode power supplies, the converter supplies a packet of charge to the output rail by first turning on one of two parallel FETs. The high-side FET is activated for a certain amount of time determined by the PWM controller. During this on time, the output voltage swings up towards the input voltage. The current flows into an inductor that is used as temporary storage for the charge. The current in the inductor rises linearly with its slope given by the formula (Vin - Vout)/L.
Once the controller switches off the high-side FET, the low-side switch is kept off for a short period. This prevents an unwanted and wasteful shoot-through of power across the two FETs. Then the low-side FET is activated for a short period and then allowed to switch on. The inductor current then begins to fall with a slope of -Vout/L until the low-side FET is turned off and the cycle begins again. As a result, the current on the output side tends to oscillate above and below an average level. Filtering by the inductor and output capacitors helps smooth the current and voltage delivered to the load.
To determine the on times of the FETs during each cycle, the PWM controller inside the converter compares the output voltage and to a reference voltage, generating an error voltage. The error signal should remain quite close to zero but will rise and fall as the load demand changes. This simple structure allows the circuitry to be realized using analog circuitry.
A key issue with any power converter is that there is a lag between changes in load demand and the resulting compensation by the PWM controller because of its discrete nature. There is an inherent tradeoff in the design of the control loop. To ensure stability, averaging is used to prevent unwanted ringing in the output voltage and a resulting failure of regulation. In general, a slower response tends to make the system more stable; but the delay in responding to changes in demand for power can lead to a loss of regulation as the PWM-based control loop attempts to keep up. An approach that attempts to compromise between these two extremes is to apply a gain correction that is proportional to the size of the error voltage. This improves responsiveness at the cost of potential instability.
A switch to a digital control strategy allows more flexibility in the design of the control strategy. For example, with the classic proportional, integral, derivative (PID) control architecture, digital or software-based implementations make it easier to tune the coefficients of the different parts of the algorithm and include additional feedback paths for better responsiveness. PID controllers are designed for use with error inputs and combine the outputs of processing blocks that apply different strategies.
The proportional term acts directly on the error signal. If the error is large, the output from this term will also be large. The integral term takes into account the longer-term action of the controller. Its output is only large if the error voltage remains large for a number of samples. The derivative terms attempts to look into the future by analyzing the rate of change of the error signal. If the error changes rapidly, the output of this term will be commensurately large. By altering the coefficients for the three terms, the controller user can easily alter the responsiveness and stability of the algorithm.
A digital strategy also makes it possible to take advantage of multi-rate sampling. Rather than sample at a constant frequency, multi-rate sampling lets the strategy adapt to rapid changes in load conditions. One way to achieve this effect with a single sampling input is to employ variable-frequency switching. If the output voltage starts to change more quickly, the controller increases the PWM frequency to adapt. However, variable-frequency switching introduces challenges for designers in terms of electromagnetic compatibility (EMC): it is easier to filter a fixed-frequency than cover a much wider frequency range.
Figure 1: Block diagram of the Intersil ZL8800.
Intersil developed its ChargeMode technology to provide a way of introducing the advantages of multi-rate sampling without the negative effects. Used in the ZL8800 dual-channel/dual-phase DC/DC controller, the technique samples the error voltage and computes the modulation signal more than once during a switching period so that the controller can adjust the timing of both edges of the PWM waveform. This technique significantly reduces group delay and therefore supports very high bandwidth operation.
The programmable nature of the ChargeMode approach makes it possible to dial in high loop gains by changing internal coefficients. The controller uses a novel strategy to overcome the instability of using just high loop gain, which localizes the effect of rapid changes in PWM timing to one or a few cycles. The effect of a sudden change in duty cycle can be compensated over the following few cycles and is performed by the ASCR block.
Figure 2: The structure of the ASCR control loop.
The compensator uses a similar feedback-based algorithm to that employed by PID controllers, but with the significant difference that the compensator has two parallel paths for processing the quantized error voltage. The fast path operates at a higher rate than the slow path and, unlike the slow path, does not include an integrator block. The fast path is used mainly to compensate for the short-term effects of a duty-cycle change. Mathematically, the compensator simplifies down to a two-pole, two-zero filter. This structure provides predictable, stable performance.
ChargeMode control with the inclusion of the ASCR digital compensator reduces the delays between the error sampling instant and the duty cycle decision. This translates to a natural phase boost at high frequencies, which brings stability and makes it possible for high-bandwidth designs. The ASCR compensator only needs to be tuned for bandwidth. There are two inputs to the ASCR block: the gain setting and a residual. However, in a wide range of output filter configurations, only the ASCR gain needs to be varied to reach the desired closed-loop bandwidth operation. Gain is responsible for the overall transient response speed, whereas the residual is a dampening factor, essentially setting the response rate of the loop. That may improve performance in highly transient-sensitive designs but the default is suitable for most systems.
Figure 3: The effect of different software parameters on impulse response.
One potential drawback of the conventional multi-rate sampling technique is the injection of switching frequency harmonics into the feedback loop due to oversampling of the error voltage. A device such as the ZL8800 employs a low-latency ripple filter in the fast path to deal with that problem. Repetitive elements of the ripple are rejected.
A further advantage of a software-configurable digital control loop is the ability to program device behavior after PCB assembly instead of relying on the addition of passive components such as resistors and capacitors. This provides for easier prototyping as well as system tuning during manufacture. The PowerNavigator software written by Intersil for the ChargeMode-technology devices enables simple configuration of the power controller and provides guidance on suitable settings for gain and other parameters.
Thanks to the combination of digital control and software programmability, the ZL8800 represents one of a growing class of power converters that will further boost energy efficiency.
