As the adoption of the Internet of Things applications gathers momentum, so does the pressure on the embedded development community to juggle the balance of available compute resource, latency, cost, and size for each design. The focus on cloud connectivity is also becoming seen as a challenge for some developments due to their real-time nature, leading to a hybrid “fog” computing approach. Provisioning local gateways to provide an on-premise cloud aspect to the fog approach might require fairly high compute demands and algorithm processing. The challenge for many designers tasked with the development of a gateway appliance is to understand the diversity of its compute requirements. Some applications, particularly those found in industrial IoT deployments, might involve fairly complex motor control or vision processing tasks. For these the requirements not only demand a high level of compute capability, but also a real-time deterministic behavior. While high end CPUs have typically been the device of choice, there are a number of other devices that are gaining the attention of developers. One of these is the field programmable gate array (FPGA), which is fast gaining momentum due to its hard deterministic capabilities.
Those unfamiliar with using FPGAs are faced with many myths as to the complexity, cost and power hungry nature of these devices. Many developers have felt that FPGAs might only suit highly specialized, high-cost military systems, but the current situation is well removed from that scenario. In today’s cloud connected world, the largest application for FPGAs is in data center applications where they are used for image recognition searches using neural network deep-learning techniques, in addition to accelerating search capabilities.
There is no doubt that embedded developers that are well versed in building microcontroller or microprocessor based systems will be rather daunted by the learning curve ahead of them when considering using an FPGA. To most, the notable difference will be moving from a software-based thought process to a hardware “gate” approach. Considered to be the closest thing to designing custom ICs that will do exactly what you want of them, an FPGA is essentially a blank canvas of general purpose gates and cells, the fabric that is programmed or connected together using a hardware descriptive language (HDL) (Figure 1). Electronics engineers who studied digital logic will feel at home very quickly with the basic concepts behind an FPGA, while others might find an online refresher course on the subject useful. It is worth mentioning that a good introduction to using FPGAs is the book Programming FPGAs by Simon Monk.
Figure 1: Functional block diagram of an FPGA device.
As the use of FPGAs gains momentum in a wide range of applications, so does the availability of information about them. This has mainly been fueled by the leading FPGA vendors, who have invested heavily in providing free open source software tools to help define and speed up the design flow process. Integrating an MCU within the FPGA fabric to create an FPGA system-on-chip (SoC) device has further helped to manage and integrate an FPGA into end applications. Greatly simplifying the learning and development process has contributed to the use of FPGAs in a broader range of applications, and the growth of the open community forums. Adoption of FPGAs within the maker community is also responsible for driving interest in their capabilities, and has contributed to a number of crowd funded FPGA evaluation board projects such as Mojo and Papilio. FPGA manufacturers have also worked hard at making designs far more accessible through the creation of development kits and evaluation boards that are well supported in the wider open source community. Together all of these initiatives have created a wealth of technical information and support resources that help encourage designers to contemplate their first FPGA design.
An example of such an evaluation board is Microsemi’s SmartFusion2 Starter Kit, shown in Figure 2.
Figure 2: SmartFusion2 Starter Kit.
Comprising a system-on-module (SOM) that contains the Microsemi SmartFusion2 FPGA SoC device with associated memory and clocks, and a SmartFusion2 baseboard that hosts a prototyping area, power converters and power management ICs, the Starter Kit provides a complete platform from which to embark on your first design.
The FPGA SoC device features a 32-bit ARM® Cortex®-M3 microcontroller core that is implemented within the FPGA fabric as a microcontroller sub-system (MSS). It is supported with 64 MB DDR memory and 16 MB flash, and is capable of running up to 142 MHz. Figure 3 illustrates a functional block diagram of the SmartFusion2 SOM.
Figure 3: Functional block diagram of the SmartFusion2 system-on-module.
The SOM also includes a JTAG interface, a watchdog timer, an Ethernet interface and a host of GPIO and serial (I2C, CAN, SPI and UART) interfaces. The full scope of the baseboard’s connectivity and user I/O features can be seen in Figure 4. The size of the FPGA fabric is model dependent and ranges from 6060 to 56520 logic elements. The SoC code runs a uClinux kernel, which further aids the development process by providing access to the full range of Linux tools, including networking utilities such as SSH, FTP and Telnet.
Figure 4: SmartFusion2 baseboard functional block diagram.
When it comes to programming the FPGA SoC, Microsemi’s design flow tool, Libero, is available for free download from the Microsemi website. Also included in the kit is the complete FPGA SoC and board set up as a Libero project. Libero integrates the design flow process of the FPGA design together with the embedded application development, as illustrated in Figure 5.
Figure 5: Libero integrates the traditional FPGA design flow with the microcontroller firmware development.
A Libero quick start guide serves as a good introduction to using Libero and the overall design flow process. A key part of Libero is the System Builder wizard (Figure 6), which assists developers in the architecture design process by asking a series of questions that help shape the basic system requirements, configuration options, and if required, add extra peripherals to the fabric.
Figure 6: Libero System Builder wizard – example setting of clock functions within the MSS.
In keeping with traditional development practice, a modern interpretation of a “Hello World” first program is implemented with a flashing LED design project. Fully documented in this tutorial, the document guides the engineer through the design flow process in achieving this basic design function. Figure 7, a screen capture from the tutorial, highlights the assignment of the output signal to the nominated GPIO pin that has an LED attached to it on the baseboard.
Figure 7: Assignment of GPIO pin in blinking LED example.
Conclusion
FPGAs have a lot to offer developers in terms of raw compute capability, design flexibility and performance per watt. Previously seen as complex-to-program, power hungry and expensive devices, they have matured a lot in the recent past as more and more commercial applications are drawing on their broad range of capabilities. It is recognized that there is a reasonable learning curve before an engineer might be creating complex neural network designs. However, taking the first steps has become so much easier thanks to the availability of development tools as described in this article.
