A floating-point hardware unit, when added to a CPU core for inline execution of instructions, is shown to improve motor control efficiency compared to traditional fixed-point MCU solutions.
With a growing focus on using energy-efficient technology, engineers increasingly are moving their control designs to the more efficient three-phase Brushless DC motor (BLDC) and Permanent Magnetic Synchronous motor (PMSM). Motor control algorithms for these motors often employ vector and sensorless vector control involving complex transformations and control loops for speed and position. Industrial applications generally employ a sensor-based control because higher accuracy is required, while consumer product applications, due to their cost-sensitive nature, generally use sensorless formulations.
Vector control provides efficient and accurate control of motor speed and torque. This is accomplished by decoupling the three-phase stator currents of AC electric motors into a flux component and a torque component. As a result, torque and flux can be controlled directly (similar to a DC motor) so that fast dynamic response and excellent steady-state performance can be achieved. In fact, vector control enables the performance of BLDC motor drives to be comparable or even superior to that of DC motor drives.
Sensorless vector control (SVC), which reduces cost by eliminating the speed sensor from the design, makes estimates of the motor’s speed and the position of the rotor from the observed stator currents. SVC uses complex coordinate transformations and motor mathematical models, which require a great deal of calculation. Thus SVC, like VC, necessitates a fast MCU with high computing capability.
Until recently, several factors prevented these advanced motor control techniques from gaining wider acceptance: (1) complicated theoretical mathematical modeling, (2) involved implementation strategy, and (3) traditional micro controllers (MCU) and Digital Signal Processors (DSP) implementing vector control. MCUs and DSPs use fixed-point formulation because these devices usually do not have a hardware floating-point unit (FPU).
It is reasonable to conclude that a hardware floating-point unit would make vector control implementation much simpler and faster because the multiplication, division, and trigonometric functions, which are very common in vector control algorithms, can be more efficiently carried out using floating-point values. But since engineers prefer to design on the basis of knowledge rather than assumption, this article will provide performance test data comparing an implementation using Renesas’ floating point MCU RX series with a design that uses a fixed-point MCU.
We will demonstrate that solutions using an embedded FPU provide easier development, higher efficiency, and reduced power usage on BLDC and PMSM motors. Specifically, we will discuss several key computations using fixed-point and floating-point implementation and show how the FPU provides an advantage with regard to PI and PID control loops, Clarke and Park transforms, ADC measurements converted to current values, and encoder data processing.
Key Computational Areas
For testing and analysis purposes we will focus on four key computation areas where the FPU can have an impact.
The first area is the PID and PI loops for the current and speed variables. A PID (proportional–integral–derivative controller) is the most commonly used feedback controller in industrial control systems. A PI Controller (proportional-integral controller) is a special case of the PID controller in which the derivative (D) of the error is not used.
Measurements performed with the Renesas RX62N development platform, for two current controllers and one speed controller implemented as PI loops, are shown in Table 1 below. The FPU-based implementation provides a definite advantage in CPU bandwidth and significant improvement in code size.
Fixed-Point Method
FPU Method
Ratio
CPU bandwidth (μsec)
3.5
2.75
0.79
Code size (bytes)
237
134
0.57
Table 1: Test comparison for PI Loops.
The second area is the coordinate transformations known as the Clarke and Park transforms. However, a bit of background is necessary. The goal of vector control formulation is to equivalently transfer the three-phase AC motor into DC, and then control the AC motor like a DC motor to directly control motor flux and torque.
To transfer three-phase currents into two phase DC currents, the first transformation is known as the Clarke transformation, shown as αβ→abc In Figure 1 below. It converts the three balanced currents in the three-phase stator frame into two phase-balanced currents in an orthogonal stationary frame. This occurs in the same plane as the stator frame, but the angle between the two axes is 90 degrees instead of 120 degrees. The transformation equation is given in Figure 1, bottom left.
The second transformation dq→αβ is called a Park transformation and is given by the equation in Figure 1 at the lower right. It transfers the stationary frame to the rotor frame to make the AC currents into DC currents. Also in Figure 1, F is the Magneto Motive Force, and θ is the angle between the d-axis and the α-axis, also known as the rotor angle.
Figure 1: Clarke and Park Transforms Used in Vector Formulation.
We performed measurements for the Clarke and Park transformations combined, and the results are shown in Table 2. One can see a significant improvement in CPU bandwidth, as well as in code size.
Fixed-Point Method
FPU Method
Ratio
CPU bandwidth (μsec)
10.7
6.55
0.61
Code size (bytes)
173
89
0.51
Table 2: Test comparison for Clarke and Park Transformations.
The third area is the angle estimation based on current measurements. These calculations are quite involved and the results are shown in Table 3 below. In this case, CPU bandwidth has good improvement, while the code size has small improvement.
Fixed-Point Method
FPU Method
Ratio
CPU bandwidth (μsec)
11
6.8
0.62
Code size (bytes)
119
93
0.78
Table 3: Test comparison for Position Estimation.
The fourth area is the conversion of ADC measurements into proper current values. Results are shown below in Table 4. Again, we see an improvement for both measurements.
Fixed-Point Method
FPU Method
Ratio
CPU bandwidth (μsec)
2.65
1.9
0.72
Code size (bytes)
83
49
0.59
Table 4: Test comparison for Sensor Measurements.
For the overall test, we implemented a complete sensorless vector control algorithm in fixed-point and FPU format for the Renesas RX62N devices. Using our HEW tools to compile and download the algorithm code into the flash on the Renesas RX62N device, and using its development board, we tested the complete algorithm for CPU bandwidth and code size. Results are shown in Table 5. For the CPU bandwidth, an improvement of nearly 35 percent is achieved, while the code size is reduced nearly 45 percent. In general, then, we found that the FPU makes vector control transformation, as well as the position and speed estimation, easier and more accurate. It should be noted that the RX62N has a very simple FPU with only eight instructions, yet its impact is very notable for the motor control algorithms.
Fixed-Point Method
FPU Method
Ratio
CPU bandwidth (μsec)
40
26
0.65
Code size (bytes)
13816
7597
0.55
Table 5: Test comparison for Overall Algorithm.
Renesas FPU-enabled MCUs
Lets take a closer look at the resources available to the Renesas MCU used in our tests. The Renesas RX600 CPU architecture is a Complex Instruction Set Computing (CISC) architecture with 16 general-purpose, 32-bit registers and 9 control registers to handle fast interrupts. Additionally, the architecture has a memory-protection unit, on-chip debug, DSP instructions (48-bit and 80-bit MAC, barrel shifter) and a hardware divide.
The RX600 core has a single-precision 32-bit floating-point unit, which is IEE-754-compliant. The FPU is tightly connected to the CPU sharing the same registers (see Figure 2). Competing architecture must go through the extra step of loading operand values into the general registers first and then move them into the floating point’s dedicated registers. The results of the floating-point unit are subsequently moved to the dedicated register, and then back to the general registers to be stored into memory.
Figure 2: RX600 FPU implementation uses general registers to execute all instructions.
Compared to earlier CISC CPUs, the RX CPU achieves about four times the arithmetic computation performance, namely 165 DMIPS (Dhrystone 7 MIPS). In particular, 32-bit multiplications can be performed in, at best, a single cycle (divisions require 2 to 8 cycles), and thus vector calculations for motor control can be performed faster. Once the motor control algorithms are developed on PCs, using high-level-abstraction tools such as Matlab, they can be directly ported to the FPU for further testing and check out on the hardware platform.
Summary
In summary, a floating-point hardware unit, when added to a CPU core for inline execution of instructions, brings higher performance and simpler software development to embedded applications such as motor control. Performance testing generated data for comparing this implementation with a design that uses a fixed-point MCU.
These experiments demonstrated that the CPU bandwidth usage of the FPU SVC is reduced significantly in comparison with the fixed-point SVC, and the code size of the FPU SVC is half of the fixed-point SVC, which makes it possible to use an MCU with smaller flash size, thus lowering the cost.
Hence the data demonstrates that adding an FPU in an MCU enables more computationally advanced algorithms that can help improve motor control efficiency and save energy while extending system capabilities.
What is more, creating the code from simulations is easy because all code is written in C. When a programmer finishes the code, and a system engineer is looking at the code, it is easy to understand the code as well as the impact of changing variable values.
As the improvements in this article clearly show, FPU-based algorithms should be seriously considered in your future motor control implementations. (https://www.renesas.com/en-us/#motorcontrol)
