Medical and industrial applications continue to gather more data, and this need will continue to grow as devices and systems get more connected, from wearable ECG monitors to predictive maintenance applications in factory automation. However, data is only as valuable as its accuracy, and to this end successive-approximation-register, analog-to-digital converters (SAR-ADC) promise successful and accurate digital results for a given analog input signal. This is particularly true when used in combination with the proper driver operational amplifier (op amp).
For medical and industrial monitoring, accuracy and precision is critical. The SAR-ADC produces a specified number of bits. However, if the input signal is unstable due to noise or oscillation, the converter can only reliably produce the input signal’s instabilities. The challenge is to insure the analog system noise and op amp bandwidth complement the SAR-ADC.
This article briefly discusses the design of the supporting anti-aliasing filter and the proper selection of the complementary op amp. It concludes with two final designs. Design number one will use the Analog Devices’ AD4003BRMZ, 18-bit, 2 MSPS, SAR-ADC and Analog Devices’ ADA4940-1ACPZ-R7, fully differential op amp.
Design number two will use Texas Instruments’ ADS8860IDRCT, 16-bit, 1 MSPS, SAR-ADC and Texas Instruments’ THS4531ID, fully differential operational amplifier. Please note, simulation and bench validation are the final steps in this design process.
The key to understanding the dynamics behind the SAR-ADC/amplifier interface is to break the design down into manageable blocks.
SAR-ADC input structure
The basic model for the SAR-ADC input structure mainly consists of two switches (SWsampl, SWconv), input switch resistance (Rswitch) and sample capacitor, Csampl (Figure 1).
Figure 1: A good working SAR-ADC input model facilitates the determination of the appropriate amplifier driver and anti-aliasing filter. (Image source: Digi-Key Electronics)
Prior to signal acquisition, the sample switch, SWsampl is open and the convert switch, SWconv, is open. The closure of SWsampl initiates a signal acquisition state, establishing the voltage and charge level across Csampl. At the end of the acquisition or sampling period (tAQU), SWsampl opens. With this action, the signal is isolated from the SAR-ADC’s input pin and the device proceeds to compare each N-bit to individually determine correct 1 or zero values.
During this acquisition period, there is an initial high-frequency voltage/current spike at the input of the SAR-ADC, which eventually settles to reflect the amplifier’s output voltage. If the Rflt and Cflt components do not exist in the circuit, the op amp must be capable of charging Csampl to less than ½ the least significant bit (LSB) by the end of the acquisition period. This requires a very-high-speed amplifier that can maintain stability with the Csampl capacitive load. This high-speed amplifier will also introduce more noise into the system and increase the system power consumption.
An alternative system is to re-insert Rflt and Cflt, which allows the use of a lower frequency amplifier. Additionally, the included R/C pair serves as an anti-aliasing filter.
The acquisition or sampling time, tAQU, and the throughput rate (tCVC) for Analog Device’s AD4003, 2 MHz sampling, 18-bit SAR-ADC are 290 nanoseconds (ns) and 500 ns, respectively (Figure 2).
Figure 2: The AD4003 3-wire without busy indicator serial interface timing diagram including status bits (SDI high). Signal acquisition, tAQU, occurs while the previous conversion results appear on the SDO output pin. (Image source: Analog Devices)
The correct driver amplifier selection is important. As a starting point, the amplifier must be unity-gain stable. Beyond that, the primary parameter to focus on during product selection is the amplifier’s slew rate.
The input signal volts-per-microseconds minimum slew rate (SRmin) is equal to p*fin*Vout-pp*10-6. For instance, if the frequency and output peak-to-peak voltage (Vout-pp) are 500 kHz and 2 volts, respectively, the signal slew rate is 1.256 volts/microsecond (V/µsec). A good rule of thumb is to select an op amp with a slew rate that is greater or equal to 2*SRmin. The ADA4940-1’s specified slew rate is 90 V/µsec.
Determining the value of Cflt
The role of Cflt is threefold: to absorb the high-frequency transients at the beginning of the acquisition time, to provide ample charge for the input of the SAR-ADC, and to stabilize the SAR-ADC input voltage at the end of the acquisition time. This is possible when the value of Cflt is at least 10 times higher than the value of the SAR-ADC sampling capacitor, Csampl. This ensures that 95% of the required charge is available for the sampling capacitor.
For the Analog Devices’ AD4003, Cflt must be equal to or greater than 400 picofarads (pF) (see Figure 1 again). In this article’s first design, using the AD4003, the value of Cflt is 500 pF. The Cflt process material should be C0G or NPO for their high Q, low temperature coefficient, and stable electrical characteristics under varying voltages, frequency and time.
The Rflt resistor has two functions. The first function is to isolate the output of the amplifier from the high capacitive load. The second function is to create a first-order, anti-aliasing filter.
Determining the value of Rflt as an isolation agent and anti-aliasing filter
One of the goals of the combination of the driver and the operational amplifier is to create a stable amplifier by isolating the load capacitance from the output of the driver amplifier. A resistor between the amplifier load capacitance and the amplifier output accomplishes this task. One of the constraints on the selection of the proper resistor is to ensure that the amplifier circuit is stable. The Rflt/Cflt pair adds an additional pole and zero to the amplifier’s open-loop transfer function (Figure 2).
Figure 3: The ADA4940-1’s open-loop gain versus frequency curve. Rflt and Cflt change the amplifier’s open-loop gain curve. For stability, the rate of closure of open-loop gain (Aol) and closed-loop gain (Acl) curves must be 20 dB/decade. (Image source: Digi-Key Electronics)
Amplifier stability occurs where the open-loop gain and closed-loop gain curves intersect. The circuit will be stable if the rate of closure of these two curves is 20 dB/decade (see Figure 2 again). The circuit will be unstable if the rate of closure of these two curves is 40 dB/decade.
Equation 1 shows the correct formula for Rflt.
Where GBWP is the amplifier’s gain-bandwidth product
Equations 2 and 3 provide the pole (fpx) and zero (fpz) corner frequencies.
Where Ro is the amplifier’s open-loop output impedance.
The values of Rflt and Cflt for the first design using the ADA4940-1 and AD4003 are equal to 15 W and 500 pF. The question at this point is: What is the cut-off frequency of this first order, anti-aliasing filter?
The response of this first order, anti-aliasing filter is dependent on the values of Rflt and Cflt. The variable of the corner frequency for this filter is fflt (Equation 4).
Rflt and Cflt attenuate noise in the analog path at a rate of 20 dB/decade above 7.6 MHz. Note that fflt is equal to fzx.
The definition of the amplifier bandwidth is contained in Equation 1, which uses the GBWP specification. However, there is more to the amplifier selection process. Characteristics such as the amplifier settling time and noise are on the critical list for consideration.
Amplifier selection
The settling time of the amplifier combines with the settling time of the Rflt/Cflt network to produce the composite system settling time.
One of the goals of the combination of the driver operational amplifier, Rflt, and Cflt, is to create an environment where the signal settles to a voltage that is less than or equal to 0.5 LSB of the SAR-ADC. As the resolution increases with the SAR-ADC the settling tolerance becomes smaller and smaller (Table 1).
10
0.0488281%
8
12
0.0122070%
9
14
0.0030518%
11
16
0.0007629%
12
18
0.0001907%
13
20
0.0000477%
15
22
0.0000119%
17
24
0.0000030%
18
Table 1: As the number of SAR-ADC bits increase, the accuracy of the sampled signal also increases. (Image source: Digi-Key Electronics)
In the table above, the calculation of the 0.5 LSB limit is equal to 100*0.5/2N, where N is equal to the SAR-ADC number of bits. The AD4003BRMZ-ND is an 18-bit SAR-ADC, so per the Table, the required number of time constants for an 18-bit ADC is 13.
The SAR-ADC input signal must settle within the converter’s tAQU time. For the ADA4003 converter this is a minimum of 290 ns.
The ADA4940-1, 0.1%, 2 volt step settling time is 37 ns. Therefore, we have a good chance of sampling within 290 ns, the acquisition time, tAQU, of the ADC.
The final key issue to consider is the system noise.
System noise
It is optimum to have the noise contribution of the amplifier at least five times lower than the SAR-ADC noise. The specification for SAR-ADC noise is SNR or signal-to-noise ratio. The SNR specification units are decibels or dB.
Where V1/f_AMP_PP is the peak to peak flicker noise in rms units, en_RMS is the broadband amplifier noise, f-3dB is the 3 dB bandwidth of the Rflt/Cflt filter.
Design #2
Design number two uses the Texas Instruments’ ADS8860IDRCT, 16-bit, 1 MSPS, SAR-ADC and THS4531ID, fully differential op amp. The basic model for the SAR-ADC input structure also consists of two switches (SWsampl, SWconv), input switch resistance (Rsw) and sample capacitor, Csampl (Figure 4).
Figure 4: The ADS8860 has a pseudo-differential input stage. A good working SAR-ADC input model facilitates the determination of the appropriate amplifier driver and anti-aliasing filter. (Image source: Digi-Key Electronics)
The ADS8860 switches are similar in operation to the AD4003. Although both ADS8860 inputs acquire their respective input signals, the inverting input is limited in its input range to several hundred millivolts. Both inputs experience the same high-frequency voltage/current spike as the sampling switch (SWsampl) closes.
The tAQU and the throughput rate (1/fsample) for the ADS8860, 1 MHz sampling, 16-bit SAR-ADC is 290 ns and 1 µs, respectively (Figure 5).
Figure 5: ADS8860 3-wire operation. CONVST functions as Chip Select (Image source. Texas Instruments)
The input signal volts-per-microseconds minimum slew rate (SRmin) is equal to p*fin*Vout-pp*10-6. For instance, if the frequency and output peak-to-peak voltage (Vout-pp) are 250 kHz and 2 volts, respectively, the signal slew rate is 1.57 volts/µsec. Again, the same rule of thumb applies: select an op amp with a slew rate greater or equal to 2*SRmin. The THS4531’s specified slew rate is 200 volts/µsec.
Determining the Cflt
For the ADS8860, Cflt must be equal to or greater than ten times Csampl, or 550 pF (Figure 1). For this article Cflt is 1 nF. The Cflt process should again be C0G or NPO.
Determining the value of Rflt as an isolation agent and anti-aliasing filter
The Rflt/Cflt pair adds an additional pole and zero to the open-loop transfer function of the amplifier (Figure 6).
Figure 6: Open-loop gain versus frequency curve for the Texas Instruments THS4531. Rflt and Cflt change the amplifier’s open-loop gain curve. For stability, the rate of closure of open-loop gain (Aol) and closed-loop gain (Acl) curves must be 20 dB/decade. (Image source: Digi-Key Electronics)
The values of Rflt and Cflt for the first design, using the THS4531and ADS8860, are equal to 50 W and 1 nF, respectively (Equations 1, 2, and 3).
The response of this first order, anti-aliasing filter is dependent upon the values of Rflt and Cflt. The variable of the corner frequency for this filter is fflt (Equation 4). Rflt and Cflt attenuates noise in the analog path at a rate of 20 dB/decade above 1.13 MHz. Note that fflt is equal to fzx.
Amplifier selection
The settling time of the amplifier combines with the settling time of the Rflt/Cflt network to produce the composite system settling time.
One of the goals of the combination of the driver operational amplifier, Rflt, and Cflt is to create an environment where the signal settles to a voltage that is less than or equal to 0.5 LSB of the SAR-ADC. As the resolution increases with the SAR-ADC, the settling tolerance becomes smaller and smaller (Table 1). The ADS8860 is a 16-bit SAR-ADC. Per the Table, the required number of time constants for a 16-bit ADC is 12.
The SAR-ADC input signal must settle within the converter’s tAQU time. For the ADS8860 converter this is a minimum of 290 ns. The THS4531’s, 0.01%, 2 volt step settling time is 150 ns. Therefore, there is a good chance of sampling within 290 ns, the acquisition time, tAQU, of the ADC.
Conclusion
As noted, data is only as valid as its accuracy. For industrial and medical applications, accuracy is critical, so successful design starts at the point of data acquisition.
This article provides the design equations to obtain the correct driver amplifier and anti-aliasing filter for SAR-ADC devices. The equations match the amplifier’s bandwidth, slew rate, and noise to the SAR-ADC’s conversion time and acquisition time to create a stable, precise system. By reviewing and understanding the design formulas, it is possible to design an SAR-ADC driver amplifier system using the products and design examples shown for reference.
Again, please note, simulation and bench validation are the final steps in this design process.
