芯片型号：CP1130

• The CP1130 is a highly integrated, very flexible multi-port and multi-rate SDH/SONET bus converter and aggregator. It can be used for bus conversion between SDH/SONET serial 155/622 Mbit/s LVDS interface and parallel 19.44/77.76 MHz Telecom Bus for backplane connections, as well as signals aggregation function between multi ports low speed signals and one or multi ports high speed signal. CP1130 supports up to four 155/622 Mbit/s LVDS interfaces and four byte-wide 19.44/77.76MHz data bus interfaces. An 8X8 STM-4/OC-12 cross connect is integrated for data transfer from any ports to any ports at STS-1/AU3 granularity.

• LVDS Interfaces

▋Four-channel CDR provides SDH/SONET LVDS 155/622Mbit/s serial interface per channel

▋Power down option of CDR per channel basis or/and whole CDR module.

▋77.76M differential LVDS reference clock input

▋Complies with ITU-T, Bellcore, and ANSI specification for jitter tolerance.

▋Complies with ITU-T, Bellcore, and ANSI specification for jitter transfer and generation if a jitter-free reference clock is applied.

▋8:1 data multiplexing/demultiplexing (MUX/deMUX) for 77.76/19.44 MHz byte-wide data processing by CDR block.

▋Frame boundary detection on the incoming data stream based on a subset of A1A2 bytes (the last two A1 bytes and the first two A2 bytes)

▋Detects loss of signal (LOS), out of frame (OOF), and loss of frame (LOF) conditions in the incoming data stream

▋Automatically insert line AIS into down stream if LOS or LOF alarm is declared.

▋Inserts A1/A2 framing pattern

▋Optionally de-scrambles the received data stream

▋Optionally scrambles the transmit data stream

▋Calculates the BIP-8 (B1) parity for current frame and compares against received B1 of the next frame.

▋A 8-bit counter accumulates B1 errors based on “word” event

▋Calculates B1 and inserts to the transmit data stream

▋Interprets the received AU-4/STS-1 payload pointer (H1/H2) and extracts the payload

▋Detects loss of pointer (AU-LOP) and path alarm indications signal (AU-AIS)

▋Automatically inserts AU-AIS when AU-LOP or AU-AIS are detected

▋Optionally inserts AU-AIS

▋Provides 108-byte FIFO per channel for both frame alignment and compensating interlink and clock phase skew

▋Frame alignment is optionally disabled.

• Telecom Bus Interfaces

▋Four-channel Telecom Bus interfaces provides SDH/SONET byte-wide 19.44/77.76 MHz interfaces per channel

▋Supports master or slave timing mode

▋Optionally inserts fixed AU4/AU3 pointer H1/H2

▋Optionally inserts H4 byte

▋Provides 108-byte FIFO per channel for both frame alignment and compensating interlink and clock phase skew

▋Frame alignment is optionally disabled.

▋Optionally performs multi-frame detection

Framer Controller

▋Provides two independent reference frame pulses for frame alignment and cross connection. The reference frame pulse for each channel is independently selectable.

• Cross Connect

▋Provides high order cross connection at STS-1/AU3 granularity.

▋Provides two independent timing planes. The timing plane for each switch element is • independently selectable.

▋Supports RS/MS overhead (TOH) cross connect independently

▋Supports uni-cast and multi-cast

▋Supports cross connect bypass

• General

▋Provides 8-bit Intel/Motorola microprocessor interface

▋Provides LVDS and Telecom Bus interface loop-back

▋1.8V/3.3V power supply

▋Supports IEEE 1149.1 boundary scan

▋Operating industrial temperature range -40℃ ~85℃

▋Maximum power consumption less then 800 mW

▋FPBGA 272 package

155/622Mbis/s backplane driver、Bus conversion、Bus aggregation